The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a method of programming a flash memory device, such as a semiconductor/oxide-nitride-oxide on semiconductor (SONOS) type electrically erasable programmable read only memory (EEPROM).
A pervasive trend in moderm integrated circuit manufacture is to increase the number of bits stored per unit area on an integrated circuit memory core that contains memory devices (sometimes referred to as memory cells), such as flash electrically erasable programmable read only memory (EEPROM) devices. For instance, a conventional semiconductor/oxide-nitride-oxide on semiconductor (SONOS) type memory device is capable of storing two bits of data in xe2x80x9cdouble-bitxe2x80x9d format. That is, one bit can be stored using a memory cell on a first side of the memory device and a second bit can be stored using a memory cell on a second side of the memory device.
An example of a conventional non-volatile SONOS-type memory cell includes a semiconductor substrate with a source and a drain (typically having N-type conductivity) formed therein. A body is formed between the source and the drain. An oxide-nitride-oxide (ONO) dielectric stack is formed above the body. A polysilicon gate electrode is formed over the ONO stack. The ONO stack includes a first or bottom dielectric layer (often referred to as a bottom tunnel oxide), a charge storing layer, and a second or top dielectric layer.
Programming of such a SONOS device can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to each of the gate, the source, and the drain of the SONOS memory cell for a specified duration until the charge storing layer accumulates charge. Such a process, with respect to a NOR architecture SONOS device is disclosed in co-owned U.S. Pat. No. 6,215,702, which is incorporated herein by reference in its entirety.
During hot electron injection, each of the charge storing cells within the charge storing layer are programmed by applying appropriate potentials to the source, drain, and/or gate electrode. The applied potentials generate a vertical electric field through the top and bottom dielectric layers and the charge storing layer as well as a lateral electric field along the length of a channel, which extends from the source to the drain, within the body. The lateral electric field causes electrons to be drawn off of the source and begin accelerating toward the drain. As electrons move along the length of the channel, the electrons gain energy and, upon attaining enough energy, jump over the potential barrier of the bottom dielectric layer and into the charge storing layer (within the respective charge storing cells) where the electrons become trapped.
While conventional hot electron injection provides control over the lateral location of the stored charge within the charge storing layer, it is nearly impossible to control the position of the deposited charge along the height dimension of the device (i.e., the position within the charge storing layer along the vertical direction). In other words, charge is stored within each charge storing cell along both a top portion of each cell (i.e., the portion adjacent the top dielectric layer) as well as along a bottom portion of each cell (i.e., the portion adjacent the bottom dielectric layer).
One of the most important concerns with EEPROM cells is data retention capability. Data retention is defined as the length of time a particular cell can retain information stored in the form of charge within the charge storing layer. Charge stored near the interface between the charge storing layer and the bottom dielectric is more easily lost during storage, especially in memory devices employing very thin bottom dielectric layers. This loss of charge occurs due to a xe2x80x9clow voltage leakage current,xe2x80x9d which arises when electrons within the charge storing layer traverse the bottom dielectric when no voltage is applied to the device. This small amount of leakage current may ultimately lead to total discharge of the cell.
Accordingly, there is an ever increasing demand to store data in memory devices, while increasing the data retention and reliability of the device.
According to one aspect of the invention, the invention is directed to a method of programming a memory device. The device can include a charge storing layer having a first charge storing cell and a second charge storing cell. The charge storing layer can be disposed between a top dielectric layer and a bottom dielectric layer. The charge storing layer can include an upper portion, which is disposed adjacent the top dielectric layer, and a lower portion, which is disposed adjacent the bottom dielectric layer. A gate electrode can be disposed over the top dielectric layer with the bottom dielectric layer being disposed over a substrate having a first conductive region adjacent the first charge storing cell and a second conductive region adjacent the second charge storing cell. The method includes programming the first charge storing cell by selectively storing charge in the upper portion of the first charge storing cell, such that substantially all of the charge resides within the upper portion of the first charge storing cell and substantially no charge resides within the lower portion of the first charge storing cell.
According to another aspect of the invention, the invention is directed to a method of selectively storing charge within an upper portion of a charge storing layer of a non-volatile memory device. The memory device can include a charge storing layer, which is disposed between a top dielectric layer and a bottom dielectric layer. A gate electrode can be disposed over the top dielectric layer, while the bottom dielectric layer is disposed over a substrate. A source and a drain can be disposed within the substrate. The method includes performing a channel hot electron injection procedure, where the channel hot electron injection procedure is operative to write charge into at least one charge storing cell within the charge storing layer, the charge storing cell having an upper portion disposed adjacent the top dielectric layer and a bottom portion disposed adjacent the bottom dielectric layer. A soft erase procedure is performed to selectively remove charge from the bottom portion of the at least one charge storing cell.
In accordance with another aspect of the present invention, the method can include performing a verification procedure to determine whether a predetermined desired quantity of charge remains in the upper portion of the at least one charge storing cell. In response to the verification procedure, if less than the desired quantity of charge remains in the upper portion of the at least one charge storing cell, the channel hot electron injection procedure, the soft erase procedure, and the verification procedure are each repeated.